TSMC: This year's mass production of the performance-optimized 3nm N3P process is scheduled

TSMC provided an update on the present and future status of its 3nm-class processes at the second leg of its spring technology symposium series. The optical downsize of this process technology, N3P, is now scheduled to go into mass production in the second half of 2024, building on the success of their current-generation N3E process. N3P is anticipated to provide higher transistor density and improved performance efficiency compared to N3E because of that downsizing.

N3E is Produced and Producing Well

TSMC reports that they're witnessing "great" yields on the second-generation 3nm-class process technology, with N3E now in commercial production. As to the company's statement, the D0 defect density of N3E is comparable to that of N5, meaning that it matches the defect rate of the older node at the same stage of its respective lifespan. Considering the extra complexity involved in creating the last, ever-tinier iteration of FinFET technology, this is no minor accomplishment. As a result, cutting-edge clients of TSMC, like Apple, who just unveiled their M4 SoC, are able to profit from the enhanced process node quite soon.

At the ceremony, a TSMC official said, "N3E started mass production in the fourth quarter of last year, as planned." "We have seen great performance of yields on customers' products, so they did go into the marketplace as planned."

A more relaxed variant of N3B, the N3E node from TSMC does away with several EUV layers and does not use EUV double patterning at all. This results in a little reduction in production costs and, in some situations, an expansion of the process window and yields; nevertheless, some transistor density is lost in the process.

On Course for the Second Half of 2024

In the meantime, N3P has completed certification at TSMC, and the business claims that its yield performance is comparable to that of N3E. Since the N3P node is an optical shrink, processor makers may now either lower power consumption by 9% at the same frequency or boost performance by 4% at the same leakage (the prior range was between 4% ~ 10% depending on design). Additionally, the new node is intended to increase transistor density for a "mixed" chip design by 4%. According to TSMC, a "mixed" processor is one that has 20% analog circuits, 30% SRAM, and 50% logic.

Since Apple has been TSMC's sole significant client, it seems that the original N3 (also known as N3B) will have a rather quiet lifetime. In contrast, N3E will be adopted by a broad spectrum of TSMC's customers, including several of the largest chip designers in the industry. 

N3P is compatible with what came before it in terms of IP blocks, process rules, electronic design automation (EDA) tools, as well as design methodology since it is an optical shrink of N3E. TSMC anticipates that most new tape outs will use N3P rather than N3E or N3. This makes sense since N3P costs less than N3 and has better performance efficiency than N3E.

The fact that N3P is expected to be production ready in the second part of this year is its most significant feature, and chip designers should anticipate using it right away. 

The TSMC CEO said, "We have also successfully delivered N3P technology." "It has qualified, and its yield performance is around N3E. In the second part of this year, [the process technology] will begin production after receiving product customer tape outs. We anticipate most tape outs on N3 to migrate to N3P due to the [PPA benefits] of N3P.